Programmable logic array circuit having a gate to control an out

Details Programmable logic array circuit having a gate to control an out Programmable logic array circuit having a gate to control an out

1990-03-23

1991-10-22

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 307469, 307481, 364716, H03K 19177

Patent

active

050598287

ABSTRACT:
A programmable logic array circuit which has a decoder, a sense amplifier and a latching circuit. The decoder decodes an instruction code into an output signal after a first precharge timing. The latching circuit latches the output signal from the decoder immediately before a second precharge timing. The gate circuit controls an output operation of the latching circuit in response to a prescribed timing signal.

REFERENCES:
patent: 4675556 (1987-06-01), Bazes
patent: 4812685 (1989-03-01), Anceau
patent: 4831573 (1989-05-01), Norman
patent: 4876466 (1989-10-01), Kondou et al.
patent: 4886987 (1989-12-01), Usami
patent: 4912348 (1990-03-01), Maki et al.
Greenspan, "Multiple Partitioned Programmable Logic Array", IBM T.D.B., vol. 19, No. 5, Oct. 1976, pp. 1780-1781.

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