Semiconductor structures having environmentally isolated element

Details Semiconductor structures having environmentally isolated element Semiconductor structures having environmentally isolated element

1993-05-07

1995-01-31

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257508, 257692, 257693, 257698, 257700, 257704, 257774, H01L 2316

Patent

active

053861426

ABSTRACT:
A first semiconductor wafer having a semiconductor element such as a piezoresistive element or any integrated circuit located on a top surface thereof is bonded to a second semiconductor wafer so that the semiconductor element on the first wafer is received in a cavity sealed from the outside environment. The bottom surface of the second water is prepared by etching it about a mask pattern so that the pattern projects from the bottom surface, thereby forming the cavity and defining projecting surfaces which are bonded to corresponding projecting areas on the first wafer to create a hermetic seal therebetween. The second wafer is electrochemically etched to produce porous silicon with regions of non-porous monocrystalline silicon extending between the top and bottom surfaces. The porous areas are thermally oxidized to convert them to silicon dioxide while the non-porous regions bonded to bond pads of the resistive pattern on the first wafer act as extended contacts.

REFERENCES:
patent: 4437109 (1984-03-01), Anthony et al.
patent: 5166773 (1992-11-01), Temple et al.

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