Secure cryptographic logic arrangement

Details Secure cryptographic logic arrangement Secure cryptographic logic arrangement

1993-10-29

1994-11-15

Swann, Tod R.

Cryptography

Key management

Having particular key generator

380 50, 380 28, 380 2, H04K 100

Patent

active

053655915

ABSTRACT:
A secure cryptographic logic arrangement immediately halts the processing of its internal processors upon detection of a single fault. The cryptographic logic arrangement has an arithmetic logic unit, permuter, and a non-linear combiner. A total self-checking controller monitors each of the arithmetic logic unit, permuter, and non-linear combiner to determine whether a fault has occurred in any one of its internal processors. The total self-checking controller employs a scheme of transmitting a pseudorandom signal to each of the internal processors and compares a phase of the pseudorandom signal received back from each of the internal processors to determine whether a fault exists.

REFERENCES:
patent: 4543646 (1985-09-01), Ambrosius, III et al.
patent: 4987595 (1991-01-01), Marino, Jr. et al.
patent: 5144664 (1992-09-01), Esserman et al.
patent: 5222141 (1993-06-01), Killian
patent: 5303293 (1994-04-01), Bettenhausen
Gillett, J. B.; "Checking Data Encryption Engines"; IBM Technical Disclosure; vol. 25, No. 9; Feb. 1983.

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