Method of manufacturing a semiconductor memory device

Details Method of manufacturing a semiconductor memory device Method of manufacturing a semiconductor memory device

1987-04-28

1988-11-15

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 52, H01L 21385, H01L 21425, H01L 2994

Patent

active

047849690

ABSTRACT:
A method of manufacturing a semiconductor memory apparatus comprising a memory cell structure consisting of a transistor and capacitor. The method comprises the steps of forming a groove in the capacitor-forming region of a semiconductor substrate, forming a capacitor insulating film on the surface of the semiconductor substrate, including the inner surface of the groove, providing first and second contact holes in the capacitor insulating film, forming a first conductive film over the entire surface of thus produced structure, patterning the first conductive material, thereby providing a capacitor electrode covering the inner surface of the groove and first contact hole, and an interconnection electrode covering the second contact hole, forming a first interlayer insulating film over the surfaces of the capacitor electrode and interconnection electrode, forming a gate insulating film on that portion of the surface of the semiconductor substrate which lies between the capacitor electrode and interconnection electrode, forming a second conductive film over the entire surface of thus produced structure, and back-etching the second conductive film, to form a gate electrode on the gate insulating film which lies between the capacitor electrode and interconnection electrode.

REFERENCES:
patent: 4658283 (1987-04-01), Koyama
'85 IEDM Digest of Technical Papers, "Buried Storage Electrode (BSE) Cell for Megabit DRAMS", p. 710; M. Sakamoto et al.; Dec. 1985.
IE.sup.3 Electron Device Letters, "A MOS Transistor with Self-Aligned Polysilicon Source-Drain", vol. EDL-7, No. 5, p. 314; T-Y, Huang et al.; May, 1986.

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