Manufacture of the fieldless split-gate EPROM/Flash EPROM

Details Manufacture of the fieldless split-gate EPROM/Flash EPROM Manufacture of the fieldless split-gate EPROM/Flash EPROM

1993-12-02

1995-01-31

Thomas, Tom

Fishing, trapping, and vermin destroying

437 45, 148DIG116, H01L 21266

Patent

active

053858565

ABSTRACT:
A device and method of manufacturing the device comprising a self-aligned, split-gate EPROM/Flash EPROM array device. Ions are implanted into locations in a doped well in a substrate to form buried bit lines, a forming a thick dielectric over the implanted ions, implanting a first threshold voltage V.sub.T1 dopant into the doped well, formation of a first polysilicon layer on the silicon dioxide layer, forming an inter polysilicon layer on the surface of the first polysilicon layer on the device, patterning that layer by forming a mask with openings and etching through the openings in the mask, forming a second polysilicon layer on the inter polysilicon layer, forming a mask and etching portions of the second polysilicon layer to form word lines therein, and etching portions of the first polysilicon layer and the inter polysilicon dielectric to form a stacked gate beneath the word lines with a trough etched down into the well in the space defined within the buried bit lines and the second polysilicon layer, and implanting an isolation implant into the trough, whereby preliminary manufacture of the device is completed.

REFERENCES:
patent: 5156990 (1992-10-01), Mitchell
patent: 5158902 (1992-10-01), Hanada
patent: 5236853 (1993-08-01), Hsue
patent: 5273926 (1993-12-01), Tigelaar

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