Priority controller

Details Priority controller Priority controller

1983-06-17

1986-09-02

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 304

Patent

active

046099956

ABSTRACT:
A priority controller includes a pair of read only memories and a register. The register stores information identifying a request circuit to which priority has recently been granted. Corresponding locations of the two read only memories store identical data for determining priority. These read only memories are alternately enabled in accordance with the value of the most significant bit position of the information stored in the register. One of the read only memories is addressed by a first address signal consisting of the lower two bits of the register information and request signals REQ0-REQ7 supplied from eight request circuits. The other of the two read only memories is addressed by a second address obtained by exchanging the positions of the signals REQ0-REQ3 of the first address with signals REQ4-REQ7 of this first address. The information produced by the read only memory which is enabled indicates the request circuit to which priority is to be granted.

REFERENCES:
patent: 3925766 (1975-12-01), Bardotti et al.
patent: 4009470 (1977-02-01), Danilenko et al.
patent: 4121285 (1978-10-01), Chen
patent: 4271467 (1981-06-01), Holtey
patent: 4390944 (1983-06-01), Quackenbush
patent: 4394728 (1983-07-01), Comfort et al.
patent: 4408300 (1983-10-01), Shima

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