Stacked DRAM poly plate capacitor

Details Stacked DRAM poly plate capacitor Stacked DRAM poly plate capacitor

1993-09-01

1994-11-15

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437233, 437238, 437919, H01L 2170

Patent

active

053648137

ABSTRACT:
An integrated circuit capacitor is formed on a semiconductor substrate by forming an insulating layer over the substrate, forming a sacrificial layer on the insulating layer and patterning it. A first polysilicon layer is formed in an opening in the sacrificial layer which is then removed. A second insulating layer is formed over the conducting layer and the exposed substrate. A second polysilicon layer, and a third insulating layer are formed. A mask is formed over the first polysilicon layer. A polysilicon oxidation product is formed in place of the second polysilicon layer away from the first polysilicon conducting structure. A mask is formed over the surface of the device, etching through the mask to the substrate and the second polysilicon layer. Metallization is deposited onto the surface of the mask and into the openings therein. The polysilicon layers are conductive.

REFERENCES:
patent: 4742018 (1988-05-01), Kimura et al.
patent: 5116776 (1992-05-01), Chan et al.
patent: 5198386 (1993-03-01), Gonzalez
patent: 5227325 (1993-07-01), Gonzalez et al.
patent: 5284787 (1994-02-01), Ahm

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