Method of manufacturing a semiconductor memory device with multi

Fishing – trapping – and vermin destroying

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437 60, 437919, H01L 2170, H01L 2700

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active

053648110

ABSTRACT:
A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

REFERENCES:
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patent: 4994893 (1991-02-01), Ozaki et al.
patent: 5028990 (1991-07-01), Kotaki et al.
patent: 5047817 (1991-09-01), Wakamiya et al.
patent: 5049517 (1991-09-01), Liu et al.
patent: 5053351 (1991-10-01), Fazan et al.
Wakamiya et al, "Novel Stacked Capacitor Cell for 64Mb DRAM", 1989 Symposium on VLSI Technology, pp. 69-70.
Kawamoto et al, "A 1.28 .mu.m.sup.2 Bit Line Shielded Memory Cell Technology for 64Mb DRAMs," 1990 Symposium on VLSI Technology, pp. 13-14.
Application No. 07/364,033 dated Jul. 10, 1991 to Wakamiya et al.

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