MOS Analog switch driven by complementary, minimally skewed cloc

Details MOS Analog switch driven by complementary, minimally skewed cloc MOS Analog switch driven by complementary, minimally skewed cloc

1983-02-10

1985-04-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307443, 307452, 307579, H03K 1716, H03K 17687, H03K 19096

Patent

active

045089833

ABSTRACT:
An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

REFERENCES:
patent: 4066919 (1978-01-01), Huntington
patent: 4069429 (1978-01-01), White et al.
patent: 4198580 (1980-04-01), Culmer
patent: 4361769 (1980-11-01), Hatchett et al.
patent: 4393318 (1983-07-01), Takahashi et al.
patent: 4467227 (1984-08-01), Lewyn et al.
patent: 4479216 (1984-10-01), Krambeck et al.

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