Method for the manufacture of gate electrodes formed of double l

Details Method for the manufacture of gate electrodes formed of double l Method for the manufacture of gate electrodes formed of double l

1985-03-08

1987-02-03

Newsome, John H.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427 85, 427 93, B05D 512, C23C 1600

Patent

active

046408444

ABSTRACT:
A method for manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon. The polycystalline silicon is deposited in undoped fashion before the metal silicide and the doping of the silicon is obtained through the production of the source/drain-zones through ion implantation and a subsequent high temperature step. The method permits the problem-free manufacture of polycide-gates with n.sup.+ - and p.sup.+ -polysilicon on a chip without increased technological expense. Planarization is facilitated through the thin gate layers. The method is used in the manufacture of highly integrated CMOS-circuits.

REFERENCES:
patent: 4525378 (1985-06-01), Schwabe et al.
J. Vac. Sci. Technol., 17 (4), Jul./Aug., 1980, "Refractory Silicides for Integrated Circuits" by S. P. Murarka, pp. 775-792.
J. Electrochem. Soc., vol. 129, No. 6 (1982), "Electrical Properties of Composite Evaporated Silicide/Polysilicon Electrodes", by C. Koburger et al., pp. 1307 to 1312.
Digest of Technical Papers of the 1983 Symposium on VLSI Technology, Hawaii, by Fukumoto et al., "A New MoSi.sub.2 /Thin-Poly Si Gate Process, pp. 98/99.

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