Multi-processor system responsive to pause and pause clearing in

Details Multi-processor system responsive to pause and pause clearing in Multi-processor system responsive to pause and pause clearing in

1987-01-05

1989-02-07

Chan, Eddie P.

Boots, shoes, and leggings

G06F 930, G06F 1516

Patent

active

048036200

ABSTRACT:
A multi-processor system including a main storage for storing instructions and data, a master processor for supplying to a slave processor data required for the processing to be executed by the slave processor and commanding initiation of the processing, the master processor further operating to test the operation state of the slave processor and perform processing by utilizing the result of the processing executed by the slave processor. The slave processor initiates the processing under the command of the master processor and operates to inform of the master processor of completion of the processing. The slave processor operates to execute a pause instruction for suspending temporarily activation of processing for a succeeding instruction and setting a pause indication at an indicator of the slave processor. When the pause indication is set in the slave processor, the master processor operates to reset this indication to release the slave processor from the pause state. When the pause state indication is not set, the master processor executes a clearing instruction supplied from the main storage for suspending the function to activate the succeeding instruction. The slave processor also operates to set at the indicator an indication instruction indicating completion of execution of the succedding instruction. The master processor functions to reset the indication of completed execution of instruction set at the slave processor and otherwise execute an indication resetting instruction for suspending activation of a succeeding instruction.

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Patent Abstracts of Japan, vol. 6, No. 195 (P-146)[1073], Oct. 5, 1982 & JP-A-57105070 (Fujitsu K.K.), 06-30-1982.

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