Memory arrangement operable as a cache and a local memory

Details Memory arrangement operable as a cache and a local memory Memory arrangement operable as a cache and a local memory

1982-12-14

1986-04-01

Thomas, James D.

Boots, shoes, and leggings

365 49, G06F 1206, G06F 1200

Patent

active

045802408

ABSTRACT:
In a memory arrangement responsive to a first address signal and comprising a buffer memory for storing a plurality of information groups, each comprising a preselected number of information blocks, and an address array for storing a plurality of second address signals each of which specifies each information block to produce the second address signals equal in number to the preselected number, the first address signal comprises a plurality of fields one of which is a specific field representative of either of first and second operation modes in which the arrangement is operable as cache and local memories, respectively. When the specific field indicates the first mode, the preselected number of the second address signals is compared by a set of comparators with the corresponding fields of the first address signal without masking to derive one of the information blocks of the information group specified by one of the fields. When the specific field indicates the second mode, the comparison is carried out with the first and the second address signals partially masked by a masking circuit.

REFERENCES:
patent: 3518631 (1970-06-01), Lindquist
patent: 4045781 (1977-08-01), Levy et al.
patent: 4047244 (1977-09-01), Finkemeyer et al.
patent: 4115855 (1978-09-01), Chiba
patent: 4163288 (1979-07-01), Vinot
patent: 4219883 (1980-08-01), Kobayashi et al.
patent: 4354232 (1982-10-01), Ryan

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