Fast scan/set testable latch using two levels of series gating w

Details Fast scan/set testable latch using two levels of series gating w Fast scan/set testable latch using two levels of series gating w

1984-03-22

1986-04-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307467, 307291, 371 25, G11C 1140

Patent

active

045800669

ABSTRACT:
A circuit of 24 transistors and 16 resistors forming an interconnected constant current source, two differential current switches, and level shifter receives scan/set test data, clock, and enablement signals for, when connected to each of the set Q and clear Q output signals of a differential feedback latch, enabling scan/set testability of such latch. Both the latch and the connected circuit, forming in aggregate a scan/set testable latch, are implementable in Emitter Coupled Logic or current Mode Logic from standard cells of gate array technology using two levels of series gating and two current sources, which standard cells are otherwise useful for the generation of other logic macros. The differential feedback latch, experiencing but a small added capacitance from the connected circuit, continues to operate fast during normal operation, but is slow in operation for scan/set test wherein the connected circuit needs overcome differential feedback loops within the latch which are still active.

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Berglund, "Level-Sensitive Scan Design Tests Chips, Boards, System", Electronics vol. 52, No. 6, Mar. 1979, pp. 108-110.
Canova et al., "LSSD Compatible D-Function Latch", IBM TDB, vol. 25, No. 10, Mar. 1983, pp. 5196-5198.

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