Method of making CMOS by twin-tub process integrated with a vert

Details Method of making CMOS by twin-tub process integrated with a vert Method of making CMOS by twin-tub process integrated with a vert

1982-06-22

1985-04-02

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29577C, 148 15, 148187, 357 42, 357 91, H01L 21265, B01J 1700

Patent

active

045078475

ABSTRACT:
A process for forming high performance npn bipolar transistors in an enhanced CMOS process using only one additional mask level. The bipolar transistor is formed using a low dose blanket implant to form the base in the substrate n-well, then applying arsenic-implanted polysilicon to form the emitter. The emitter formation involves forming a blanket polysilicon layer over the wafer, then using the additional photomask to confine the subsequent arsenic implant to the emitter, n.sup.+ and polysilicon contact regions, prior to application of aluminum metallization. The arsenic implanted polysilicon technique provides state-of-the-art bipolar processing as well as improved contact characteristics. The combined polysilicon-aluminum metallization improves step coverage, circuit reliability, and reduces the possibility of aluminum diffusion (spiking) through junctions. The n-type contact resistance is improved by virtue of being implanted with arsenic; the p-type contact resistance is controlled by the diffusion from the p.sup.+ regions which dope the polysilicon during the emitter drive-in cycle.

REFERENCES:
patent: 3609479 (1971-09-01), Lin et al.
patent: 3739238 (1973-06-01), Hara
patent: 4325169 (1982-04-01), Ponder et al.
patent: 4346512 (1982-08-01), Liang et al.
patent: 4362574 (1982-12-01), Gevondyan
patent: 4403395 (1983-09-01), Curran
patent: 4406710 (1983-09-01), Davies et al.
patent: 4420344 (1983-12-01), Davies et al.
patent: 4420872 (1983-12-01), Zaldivar et al.
patent: 4434543 (1984-03-01), Schwabe et al.
patent: 4435896 (1984-03-01), Parillo et al.
patent: 4442591 (1984-04-01), Haken
patent: 4452645 (1984-06-01), Chu et al.
Ma et al., IBM-TDB, 16 (1973) 2287.
Chin et al., IBM-TDB, 16 (1973) 1985.
Dorler et al., IBM-TDB, 24 (1981) 466.
Zimmer et al., "A Fully Implanted NMOS, CMOS, Bipolar Technology for VLSI of Analog-Digital Systems", IEEE Journal of Solid-State Circuits, vol. SC-14, No. 2, Apr. 1979, pp. 312-318.
Scott et al., "Considerations for Scaled CMOS Source/Drains" IEEE International Electron Devices Meeting 1981, pp. 538-541.
Graul et al., "High-Performance Transistors with Arsenic-Implanted Polysil Emitters", IEEE Journal of Solid-State Circuits, vol. SC-11, No. 4, Aug. 1976, pp. 491-495.
Ning et al., "Effect of Emitter Contact on Current Gain of Silicon Bipolar Devices", IEEE Transactions on Electron Devices, vol. ED-27, No. 11, Nov. 1980, pp. 2051-2055.

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