Symmetrical instructions queue for high clock frequency scheduli

Details Symmetrical instructions queue for high clock frequency scheduli Symmetrical instructions queue for high clock frequency scheduli

1998-08-24

2000-09-19

Follansbee, John A.

Electrical computers and digital processing systems: processing

Instruction issuing

712 23, 712200, 712215, 712216, G06F 1500

Patent

active

061227277

ABSTRACT:
An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that instruction queue. The dependency vector is evaluated to determine if the corresponding instruction operation may be scheduled for execution. Instruction scheduling logic in each physical queue may schedule instruction operations based on the instruction operations stored in that physical queue independent of the scheduling logic in other queues. The instruction queues evaluate the dependency vector in portions, during different phases of the clock. During a first phase, a first instruction queue evaluates a first portion of the dependency vectors and generates a set of intermediate scheduling request signals. During a second phase, the first instruction queue evaluates a second portion of the dependency vector and the intermediate scheduling request signal to generate a scheduling request signal. The second instruction queue may evaluate the portions of the dependency vector in the second phase and the first phase of the clock, respectively. In other words, the second instruction queue may operate 1/2 clock cycle off of the first instruction queue. Satisfaction of dependencies upon an instruction operation in the opposite queue may thereby propagate to scheduling of the dependent instruction operation in 1/2 clock cycle.

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