Method and apparatus for error detection and correction of data

Details Method and apparatus for error detection and correction of data Method and apparatus for error detection and correction of data

1994-12-07

1995-10-03

Beausoliel, Jr., Robert W.

Excavating

371 401, 371 404, 371 491, 364285, 3649647, 3649654, G06F 1134

Patent

active

054559391

ABSTRACT:
A method and apparatus for detecting and correcting errors in data transferred between a CPU and system memory. System memory typically has a number of dynamic random access memory (DRAM) devices that each have a block of memory cells. The DRAM also has an internal cache that contains a row of memory from a main memory block. Both the cache and block of memory cells contain vertical and horizontal parity bits. Each byte of data bits has an associated horizontal parity bit. Similarly a group of data bits having the same bit position will have an associated vertical parity bit. The parity bits are used to detect and correct errors in data transmissions between a CPU and system memory The cache includes arrays of exclusive OR (XOR) gates that can update the vertical parity bits when one or more bytes of data are written into the DRAM.

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