Logic simulator employing hierarchical checkpointing

Details Logic simulator employing hierarchical checkpointing Logic simulator employing hierarchical checkpointing

1993-10-14

1995-10-03

Kim, Ken S.

Boots, shoes, and leggings

364578, 364DIG1, 395180, 395427, G06F 1208, G06F 1134

Patent

active

054559294

ABSTRACT:
A simulator system of a digital network which may contain a memory. The system includes at least three hierarchical data storage buffers 18, 20, 24, 26 for storing the simulated network signals for simulated registers and combinatorial logic at the close of each simulation cycle. Each buffer 20, 24, 26 has a plurality of entries comprising a periodic sampling, sometimes referred to as checkpointing, of the next lower storage buffer. The system also includes a change management list 30 and a memory data array 32 for respectively storing time/address pairs and time/value pairs to identify the time, address and value of memory writes. These pairs of data are updated (i.e., checkpointed) each time a selected data storage buffer 24, 26 starts to have previously written locations overwritten by newer data.

REFERENCES:
patent: 4862347 (1989-08-01), Rudy
patent: 4924429 (1990-05-01), Kurashita et al.
patent: 5008786 (1991-04-01), Thatte
patent: 5142488 (1992-08-01), Chan et al.

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