Address formation circuit and method for continuously performing

Details Address formation circuit and method for continuously performing Address formation circuit and method for continuously performing

1993-06-30

1995-10-03

Powell, Mark R.

395162, G06F 1206

Patent

active

054559081

ABSTRACT:
In an address formation circuit for an image processing, an address formation is separately processed in parallel like a pipeline by first and second address calculation means. The first address calculation means controllable by a program calculates a head address of a macroblock, and the second address calculation means calculates addresses of pixels within the macroblock on the basis of the head address calculated by the first address calculation means. An instruction memory stores the program and a data memory and a data file memory store address moving amounts required the calculations. A sequence controller controls an exclusive hardware. Hence, a high speed memory access like a real time image processing in the address formation can be possible and, when a complicated address pattern is required, an overhead of the address formation time in the instruction processing can be prevented.

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patent: 5293596 (1994-03-01), Toyokura et al.
patent: 5309528 (1994-05-01), Rosen et al.
Reader et al., "The IIP--An Interactive Image Processor", IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, pp. 149-153 (Nov. 1981).
Haraski et al., Technical Research Report CAS86-225, Electronic Information & Communication Society of Japan, Mar. 1987.

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