High performance derived local bus and computer system employing

Details High performance derived local bus and computer system employing High performance derived local bus and computer system employing

1996-08-28

1997-08-05

Donaghue, Larry D.

Boots, shoes, and leggings

395500, 395650, 395735, 364DIG1, G06F 1324

Patent

active

056551428

ABSTRACT:
An integrated processor is provided that includes a CPU core, a local bus coupled to the CPU core, and a variety of peripheral such as a memory controller, a direct memory access controller, and an interrupt controller coupled to the local bus. A bus interface unit is further provided to interface between the CPU local bus and a PCI standard multiplexed peripheral bus. The CPU core, the memory controller, the direct memory access controller, the interrupt controller, and the bus interface unit are all incorporated on a common integrated circuit chip. A local bus control unit is further provided that is capable of generating a loading signal and an address strobe signal synchronously with certain bus cycles that are executed on the PCI bus. The local bus control unit allows external peripheral devices that are compatible with the CPU local bus protocols to be connected through the PCI bus. A latch is coupled to the multiplexed address/data (A/D) lines of the PCI bus and includes a set of output lines coupled to the address input lines of the externally connected peripheral device. The external latch is latched by the loading signal. The cycle definition signals of the PCI bus are further latched within the external latch to provide memory/IO and read/write signals to the external peripheral device. The data lines of the peripheral device may be connected directly to the multiplexed address/data lines of the PCI bus.

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