Output-buffer switch for asynchronous transfer mode

Details Output-buffer switch for asynchronous transfer mode Output-buffer switch for asynchronous transfer mode

1994-05-18

1995-10-03

Hsu, Alpus

Multiplex communications

Wide area network

Packet switching

370 601, 370 61, 370 942, H04L 1256

Patent

active

054558204

ABSTRACT:
In an output-buffer switch for an asynchronous transfer mode, comprising a plurality of input buffer sections each for temporarily storing cells coming in through a respective input line, a time-division multiplexing section for time-division multiplexing the cells from the input buffer sections, and a plurality of output buffer sections each for temporarily storing the cells from the time-division multiplexing section which are meant for a respective output line, the output buffer sections each has a cell buffer, and a buffer occupancy ratio calculator which calculates an occupancy ratio of the cell buffer on the basis of the address information of the trailing and leading cells stored in the buffer. When the occupancy ratio exceeds a predetermined threshold, the calculator generates a buffer occupancy state signal. Each input buffer section has a buffer controller, an address filter, cell buffers, and a buffer selector. On receiving a buffer occupancy state signal from any output buffer section, the buffer controller controls the address filter, cell buffers and buffer selector such that cells addressed to the output buffer section, which is about to overflow, are temporarily stored in the cell buffer other than the cell buffer used when the buffer occupancy state signal is absent. These cells are fed out from the buffer when the occupancy ratio decreases to below the threshold. As a result, when any one of the output buffer sections overflows, it is recovered immediately without cells being discarded.

REFERENCES:
patent: 4964119 (1990-10-01), Endo et al.
patent: 5079762 (1992-01-01), Tanabe
patent: 5119372 (1992-06-01), Verbeek
patent: 5126999 (1992-06-01), Munter et al.
patent: 5128931 (1992-07-01), Yamanaka et al.
patent: 5283782 (1994-02-01), Takase et al.
Suzuki et al., "Output-Buffer Switch Architecture for Asynchronous Transfer Mode", International Journal of Digital and Analog Cabled Systems, vol. 2, pp. 269-278 (1989).

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