Buffer protection against output-node voltage excursions

Details Buffer protection against output-node voltage excursions Buffer protection against output-node voltage excursions

1993-09-15

1995-10-03

Hoff, Marc S.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

361 56, 361 84, H03K 190175

Patent

active

054557321

ABSTRACT:
A three-state output buffer circuit with built-in protection against power-rail corruption by bus-imposed voltages when the buffer is in its high-impedance state. In particular the invention protects the high-potential power rail of the high-Z buffer against voltages appearing at the buffer's output node which exceed the voltage of the buffer's high-potential rail. It prevents this overvoltage from finding its way to the power-rail, and thus has application to those situations where a common bus is coupled to a variety of circuits including, for example, 3.3-volt buffers and 5-volt buffers. The invention provides this protection without the "dead zone" of prior-art and related-art circuits. Furthermore, the present invention also has application where it is the low-potential power rail that needs protecting, in situations where the bus may impose voltages at the buffer's output node that are lower than the voltage of the buffer's low-potential power rail. The protection circuit utilizes a pseudo-power rail which can be used to adjust the bias on the output transistor's bulk and so to prevent a leakage path from occurring between the output node and a power rail via the output transistor source/bulk junction. To minimize or avoid a "dead zone" in the charging of the pseudo-rail, a one-way link is established directly between the power rail and the pseudo-power-rail.

REFERENCES:
patent: 5149991 (1992-09-01), Rogers
patent: 5160855 (1992-11-01), Dobberpuhl
patent: 5381061 (1995-01-01), Davis

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