Fishing – trapping – and vermin destroying
Patent
1989-09-25
1991-10-22
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 21, 437 62, 437152, 148DIG12, H01L 21336
Patent
active
050595474
ABSTRACT:
First and second single crystal silicon substrates are integrated, by means of a thermal treatment, with first and second silicon oxide films formed on surfaces of said respective first and second single crystal silicon substrates in contact with each other. More specifically, an insulating region is formed by integrating first and second silicon oxide films formed on the first and second single crystal silicon substrates. First and second semiconductor regions constituted by the first and second single crystal silicon substrates are electrically isolated by the insulating region. As a result, it is possible to reduce the width of the depletion layer generated in the second semiconductor region by the influence of the first semiconductor region in which an element is formed. A back gate region formed in the second semiconductor region and the first semiconductor region, in which an element is not formed, are held substantially at an equal potential. In this way, it is possible to improve the yield voltage characteristics between the first semiconductor region, which does not form any element, and the back gate region. The insulating region which electrically isolates the first and second semiconductor regions from each other, is formed by bonding together first and second silicon oxide films on surfaces of the first and second single crystal silicon substrates. Therefore, the process of manufacture is simplified.
REFERENCES:
patent: 4507158 (1985-03-01), Kamins et al.
patent: 4523213 (1985-06-01), Konaka et al.
patent: 4621276 (1986-11-01), Malhi
patent: 4700454 (1987-10-01), Baerg et al.
patent: 4753896 (1988-06-01), Matloubian
patent: 4778775 (1988-10-01), Tzeng
patent: 4786952 (1988-11-01), MacIver et al.
patent: 4837186 (1989-06-01), Ohata et al.
patent: 4884116 (1989-11-01), Shirai
Kimura, M., et al., Appl. Phys. Lett., 43(3), Aug. 1, 1983, pp. 263-265.
Brock, G. E., et al., IBM Technical Disclosure Bulletin, vol. 19, No. 9, Feb. 1977, pp. 3405-3406.
Hearn Brian E.
Kabushiki Kaisha Toshiba
Quach T. N.
LandOfFree
Method of manufacturing double diffused MOSFET with potential bi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing double diffused MOSFET with potential bi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing double diffused MOSFET with potential bi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-108071