Method of making a stacked 3D integrated circuit structure

Details Method of making a stacked 3D integrated circuit structure Method of making a stacked 3D integrated circuit structure

1995-06-07

1997-08-05

Dang, Trung

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Having diverse electrical device

438 26, 438109, 438456, 438977, 438619, 438406, H01L 2170

Patent

active

056542208

ABSTRACT:
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

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