Gate structure for a semiconductor memory device

Details Gate structure for a semiconductor memory device Gate structure for a semiconductor memory device

1991-04-24

1992-09-22

Hille, Rolf

357 71, 357 67, 357 55, 357 59, H01L 2968, H01L 2348, H01L 2906, H01L 2904

Patent

active

051501783

ABSTRACT:
In a semiconductor memory device of multistage gate structure, the second stage gate electrode (control gate electrode) is of superposed-layer structure of a second polysilicon layer and a high melting point layer or a silicide layer of a high melting point metal layer formed thereon. Those portions of the second polysilicon layer which are above the element forming regions have a thickness larger than 1/2 the width of grooves formed between adjacent first gate electrodes (floating gate electrodes), so that the grooves are filled with the second polysilicon layer to flatten the surfaces of those portions of the second polysilicon layer which are above the grooves.

REFERENCES:
patent: 4847673 (1989-07-01), Matsukawa
IEDM Technical Digest, p. 557 (1987), "Novel Process and Device Technologies for Submicron 4Mb CMOS EPROMs", Dec. 6 (1987), S. Mori et al.

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