Synchronous semiconductor memory device and method of controllin

Details Synchronous semiconductor memory device and method of controllin Synchronous semiconductor memory device and method of controllin

1997-03-07

2000-05-09

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365194, 36523003, 36523008, G11C 700

Patent

active

060612940

ABSTRACT:
A synchronous semiconductor memory device has a plurality of banks each including a cell array. A sensing process of the synchronous semiconductor memory device is controlled by starting a series of operations from selection of a row address to a sensing operation in response to a first external clock pulse, and synchronizing at least one event in the series of operation with a second external clock pulse subsequent to the first external clock pulse.

REFERENCES:
patent: 5471607 (1995-11-01), Garde
patent: 5473565 (1995-12-01), Kusakari

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