Silicon single crystal with no crystal defect in peripheral part

Chemistry of inorganic compounds – Silicon or compound thereof – Elemental silicon

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257610, 257611, 257913, 423325, C30B 2906, C31B 3300

Patent

active

061207497

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a technique for easily producing, by the Czochralski method, a silicon single crystal improved in the dielectric breakdown strength of oxide film in the peripheral part of a wafer without considerably lowering production efficiency.


BACKGROUND ART

Along with a recent tendency to increase the degree of integration of semiconductor circuits, elements have been becoming finer; thus, an insulating oxide film in the gate electrode portion of an MOS-LSI is becoming thinner. Even such a thin insulating oxide film is required to have a high dielectric breakdown strength and a small leakage current during operation of a device element, i.e. to have a high degree of reliability.
In this connection, a silicon wafer produced from a silicon single crystal which is produced by the Czochralski method (hereinafter referred to as the CZ method) is known to be significantly low in the dielectric breakdown strength of oxide film as compared to a wafer produced from a silicon single crystal produced by the floating zone method (the FZ method), or an epitaxial wafer produced by growth of a thin silicon single-crystal film on a wafer produced by the CZ method (Mitsumasa Koyanagi, "Submicron Devices II, 3-Reliability of Gate Oxide Film" Maruzen Co., Ltd., p70).
A crystal defect introduced during growth of a silicon single crystal according to the CZ method is known to be responsible for a degradation in the dielectric breakdown strength of oxide film. It is also known that through employment of a significantly low crystal growth rate (for example, 0.4 mm/min or lower), the dielectric breakdown strength of oxide film of a silicon single crystal produced by the CZ method can be significantly improved (for example, Japanese Patent Laid-Open (kokai) No. 2-267195).
When the rate of crystal growth is decreased from a conventional rate not lower than 1 mm/min to a rate of 0.4 mm/min or lower for improving the dielectric breakdown strength of oxide film, the dielectric breakdown strength of oxide film will be improved. However, the production efficiency of single crystals will become half or less, resulting in significant increase in cost.
In this connection, according to the conventional production of a silicon single crystal by the CZ method, in order to maximize the production efficiency of a single crystal, a single crystal is pulled at or near the critical rate inherent in the individual pulling apparatus. In a wafer produced from the thus-grown single-crystal ingot, defects are distributed in the wafer surface at a relatively uniform density from the central part to the peripheral part. Accordingly, when, for example, about 100 device chips are to be produced from a single wafer, the yield is similar between the central part of the wafer and the peripheral part of the wafer; i.e., failure rate is substantially uniform over the wafer surface.
As mentioned previously, in order to improve the dielectric breakdown strength of oxide film over the entire surface of a wafer, a single crystal must be pulled at a significantly low rate. In a single wafer, since a peripheral part thereof occupies a relatively large area, the yield of device chips from the wafer depends on yield from the peripheral part.
Accordingly, in order to improve the yield of device chips from a silicon single-crystal wafer, the dielectric breakdown strength of oxide film must be improved in the peripheral part of the wafer.
The present invention has been accomplished in view of the above-mentioned problems, and an object of the present invention is to easily produce, by the Czochralski method, a silicon single-crystal improved in the dielectric breakdown strength of oxide film especially in a peripheral region thereof without considerably lowering production efficiency, and to improve the yield of device chips produced from a single silicon wafer.


DISCLOSURE OF THE INVENTION

In order to solve the above-mentioned problems, the invention described in claims 1 and 2 is a silicon single-crystal wafer having a diamet

REFERENCES:
patent: 5248378 (1993-09-01), Oda et al.
patent: 5487354 (1996-01-01), Von Ammon et al.
patent: 5575847 (1996-11-01), Kuramouchi et al.
patent: 5728211 (1998-03-01), Takano et al.
patent: 5834322 (1998-11-01), Fusegawa et al.
Ryuta, et al. "Effect of Crystal Pulling Rate on Formation of Crystal-Originated `Particles` on Si Wafers," Japanese Journal Of Applied Physics, Part 2, 31 (1992) Mar. 15, No. 3b, Tokyo, pp. L293-L295.
Winkler, et al. "Improvement of the Gate Oxide Integrity by Modifying Crystal Pulling and Its Impact on Device Failures," J. Electrochem. Soc., vol. 141, No. 5, May 1994, pp. 1398-1401.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Silicon single crystal with no crystal defect in peripheral part does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon single crystal with no crystal defect in peripheral part, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon single crystal with no crystal defect in peripheral part will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1069256

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.