Method of preventing storage node to storage node shorts in fabr

Details Method of preventing storage node to storage node shorts in fabr Method of preventing storage node to storage node shorts in fabr

1991-11-19

1992-09-22

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437235, 437919, H01L 2170

Patent

active

051496682

ABSTRACT:
Disclosed is a semiconductor processing method of fabricating memory integrated circuitry. Word lines are defined. Alternating first and second separation regions therebetween are defined. Storage node capacitors are formed in the first regions. The width of the first separation regions is greater than the width of the second separation regions. An insulating layer is provided to a first selected thickness which is greater than one-half the width of the second separation regions to fill the second separation regions between with insulating material. The first selected thickness is also less than one-half the width of the first separation regions to provide a space within the first separation regions. Buried contacts are etched through the insulating layer. A layer of conductive material is deposited and patterned to define lower storage node capacitor plates. A capacitor dielectric and upper storage node capacitor plates above the lower storage node capacitor plates are provided.

REFERENCES:
patent: 4830977 (1989-05-01), Katto et al.
patent: 4882289 (1989-10-01), Moriuchi et al.
patent: 4977102 (1990-12-01), Ema
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5071783 (1991-10-01), Taguchi et al.
patent: 5084406 (1992-01-01), Rhodes et al.

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