Repeated ALU in pipelined processor design

Details Repeated ALU in pipelined processor design Repeated ALU in pipelined processor design

1992-10-09

1994-07-26

Gregory, Bernarr E.

395325, 395800, G06F 1300

Patent

active

053332849

ABSTRACT:
A six-stage pipeline processor comprised of the sequential stages: instruction fetch; instruction decode; first full ALU; second full ALU; Fill Register; and Write Back Register. Memory addresses are calculated in the first ALU stage and this stage presents the address along with a read command to memory at the end of the cycle. Two cycles are allowed for a data response from memory but only one intervening instruction is required to occupy the pipeline for most instruction sequences because bypass logic makes available data operands from memory at the second ALU stage with an apparent load latency of one cycle. Subtraction and other arithmetic operations are performed in the first ALU if the result is to be used by a subsequent LOAD instruction to calculate a memory address so that the result can be used by the first ALU to calculate the memory address without any intervening instruction and potential loss of overall performance.

REFERENCES:
patent: 4613935 (1986-09-01), Couleur
patent: 4725973 (1988-02-01), Matsuura et al.
patent: 4783783 (1988-11-01), Nagai et al.
patent: 4819155 (1989-04-01), Wulf et al.

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