Process for fabricating MOS transistors having anti-punchthrough

Details Process for fabricating MOS transistors having anti-punchthrough Process for fabricating MOS transistors having anti-punchthrough

1996-01-19

1996-08-27

Dang, Trung

Fishing, trapping, and vermin destroying

437 26, 437 28, 437 29, 437 45, 148DIG137, 148DIG106, H01L 21265

Patent

active

055500749

ABSTRACT:
Disclosed is a semiconductor fabrication process for fabricating MOS transistors in which ions are implanted only beneath the channel and are not overlapped with the source/drain regions so as to significantly reduce the junction capacitance of the source/drain regions for performance enhancement. The process comprises a first step of preparing a silicon substrate on which a field oxide region is formed to define an active region. In the second step, a phase-shift mask is used to define a substantially rectangular removal portion on a photoresist layer. One side of the rectangular removal portion is substantially aligned with the channel of the MOS transistor to be fabricated and the other three sides are placed within the field oxide region. In the third step, an anti-punchthrough implantation process is performed, in which ions are implanted through the removal portion of the photoresist layer to form an anti-punchthrough implant region beneath the channel of the MOS transistor; and in the final step, a gate region and source/drain regions are formed. The thus formed anti-punchthrough implant region is right beneath the channel of the MOS transistor and does not overlap with the source/drain regions. The packing density and performance of chips containing MOS transistors thus fabricated are high.

REFERENCES:
patent: 5208168 (1993-05-01), Parrillo et al.
patent: 5429956 (1995-07-01), Shell et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5444008 (1995-08-01), Han et al.
patent: 5489543 (1996-02-01), Hong

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