Processor using folded array structures for transposition memory

Details Processor using folded array structures for transposition memory Processor using folded array structures for transposition memory

1995-01-19

1996-08-13

Mai, Tan V.

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G06F 738

Patent

active

055463363

ABSTRACT:
A folded memory array structure that can be used with a folded processor array structure to make cosine transform calculations faster and more efficient. The memory elements of the folded memory array are interconnected is if an M by M element square array of single memory elements were logically folded or cut and overlain to form an N by N node subarray where each node has multiple interconnected memory elements. The subarray is than logically folded and the nodes connected by buses and switches as if the resultant array were folded along the diagonal, producing a triangular memory array structure. This transposed folded memory array is enhanced with computational elements disposed at the nodes of the array. A computational array processor is thereby formed which can perform cosine transform operations efficiently for multimedia, video, and other applications.

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IBM Technical Disclosure Bulletin, vol. 36, No. 3, Mar. 1993, E. Feig (Y) 892-0572) "Architecture for Descaling and Inverse Discrete Cosine Transforming".

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