Process for manufacturing a semiconductor device

Details Process for manufacturing a semiconductor device Process for manufacturing a semiconductor device

1993-02-23

1994-07-26

Thomas, Tom

Fishing, trapping, and vermin destroying

437189, 437194, 437197, 437203, H01L 2144

Patent

active

053326946

ABSTRACT:
A process for manufactoring a semiconductor device having a double- or multi-level interconnection structure is disclosed. The process includes steps of: forming a first level metal interconnect; then forming a first silicon oxide layer by PECVD, and forming a second silicon oxide layer by atmospheric CVD using tetraethoxysilane and oxygen containing ozone under a condition of excess ozone in which the ratio of flow-rate of ozone to flow-rate of tetraethoxysilane is about 20:1. An organic compound coating layer is formed by spin-coating accompanied by a thermal treatment. The organic compound coating layer and the second silicon oxide layer are etched-back to remove the compound oxide layer completely. A third silicon oxide layer is formed by PECVD; and forming a second level metal interconnect. A good planarization can be obtained and a failure, such as delamination or blister due to bumping, of the third silicon oxide layer can be avoided. Hence, a high yield and a high reliability of the semiconductor device having a double- or multi-level interconnection structure can be achieved.

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"A Highly Reliable Multilevel Interconnection Process for 0.6 m Cmos Devices", UTH-0359-0/91/0000-0013 C 1991 IEEE, by Y. Takata et al. Jun. 11-12, 1991 VMIC Conference, pp. 13-19.

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