Programmable sense amplifier power reduction

Details Programmable sense amplifier power reduction Programmable sense amplifier power reduction

1990-05-08

1993-09-21

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307468, 3072963, H03K 9173, H03K 301

Patent

active

052472132

ABSTRACT:
An apparatus for controlling the power consumption of a programmable logic device which has a plurality of output signals comprising a programmable switch coupled to each one of the logic signal outputs of the programmable logic device. The programmable switch may include a sense amplifier coupled to each one of said logic signal outputs; a first transistor coupled between said amplifier and ground; a latch coupled to the gate of said first transistor; a second transistor responsive to a first control signal; and an electrically erasable programmable read only memory (EEPROM) cell, coupled to said latch and responsive to a second control signal, said second transistor and said EEPROM cell providing a state signal to said latch.

REFERENCES:
patent: 4839539 (1989-06-01), Takata et al.
patent: 4930098 (1990-05-01), Allen
patent: 4942319 (1990-07-01), Pickett et al.
patent: 4963769 (1990-10-01), Hiltpold et al.
patent: 4972102 (1990-11-01), Reis et al.
Gowan et al., 12 ns, CMOS Programmable Device for Combinational Applications, Proceedings of IEEE, May 15, 1989, 5.5.1-5.5.4.

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