Method for testing interconnections

Details Method for testing interconnections Method for testing interconnections

1989-04-17

1991-06-25

Smith, Jerry

Excavating

G06F 1100

Patent

active

050273531

ABSTRACT:
A set of test vectors for input to a circuit (10) to test the integrity of each of its n interconnections (nets) 16 is generated by first ordering the nets. Thereafter, the vectors are generated by assigning the bits of each vector associated with a given net a one or zero such that the vector has a minimum weight, as compared to the vectors assigned to successive nets. Alternatively, the test vectors can be generated by assigning the bits of selected groups of vectors a one or zero such that the groups of vectors each have minimum potential weight and the vectors in the group are independent of each other. The successive groups of vectors are then concatenated to yield the test vector set.

REFERENCES:
H. Schnurmann, "Weighted Test Pattern Generation In Monte Carlo Testing of IC's", IBM TDB, vol. 15, No. 6, 11/1972, pp. 1725-1726.
"Test Generation of AC Faults Using Weighted Random Patterns", IBM IDB, vol. 32, No. 3A, 8/1989, pp. 4-6.
"Testing and Diagnosis of Interconnects Using Boundary Scan Architecture", A. Hassan, J. Rajski, and V. K. Agarwal, IEEE 1988 International Test Conference, Paper 7.1, pp. 126-137 (1988).
"Interconnect Testing with Boundary Scan", P. T. Wagner, IEEE 1987 International Test Conference, Paper 2.2, pp. 52-57 (1987).
"Electronic Chip-In-Place Test", P. Goel and M. T. McMahon, 1982 IEEE Test Conference, Paper 3.6, pp. 83-89 (1982).
"JTAG Boundary Scan Architecture Standard Proposal", Version 2.0, Joint Test Action Group, Mar. 30, 1988.

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