Semiconductor memory device having stacked polycrystalline silic

Details Semiconductor memory device having stacked polycrystalline silic Semiconductor memory device having stacked polycrystalline silic

1982-03-18

1984-11-06

Munson, Gene M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 54, 357 59, 365156, 3072388, H01L 2702, H01L 2934, H01L 2904, G11C 1100

Patent

active

044815247

ABSTRACT:
A high-density integrated circuit is disclosed, which comprises at least three stacked wiring layers, the lowest layer being formed of polycrystalline and including silicon gates of a plurality of insulated-gate field-effect transistors, one of the upper layers being formed of polycrystalline silicon and used for feeding a power supply to the transistors, and the other of the upper layers being formed of high-conductivity metal. Where the upper polycrystalline silicon wiring layer is under the metal wiring layer, it is preferably of a mesh-like pattern.

REFERENCES:
patent: 4132904 (1979-01-01), Harari
patent: 4209716 (1980-06-01), Raymond
patent: 4209797 (1980-06-01), Egawa et al.
patent: 4223333 (1980-09-01), Masuoka
patent: 4262340 (1981-04-01), Sasaki et al.

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