Semiconductor integrated circuit having region for forming compl

Details Semiconductor integrated circuit having region for forming compl Semiconductor integrated circuit having region for forming compl

1990-02-22

1991-12-10

Hille, Rolf

357 34, 357 43, H01L 2710

Patent

active

050722859

ABSTRACT:
A Bi-CMOS gate array comprises basic cells combining CMOS transistors and bipolar transistors. The basic cell is formed of a region for forming p-MOS transistors, a region for forming n-MOS transistors and a region for forming bipolar transistors. The region for forming p-MOS transistors comprises gates aligned spaced apart from each other in a first direction and p-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming n-MOS transistors comprises gates formed spaced apart from each other in the first direction and n-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming bipolar transistors comprises p-type source or drain region of the region for forming p-MOS transistors as a base region, and an n-type emitter region formed in the base region and a region for taking out the potential of substrate of the p-MOS transistor as a collector region. An npn bipolar transistor formed in the region for forming p-MOS transistors can be electrically isolated from the other p-MOS transistor and used by holding gates disposed at the opposite sides of the base region at a power supply potential.

REFERENCES:
patent: 4682202 (1987-07-01), Tanizawa
patent: 4825274 (1989-04-01), Higuchi et al.
patent: 4829200 (1989-05-01), Downey
patent: 4868626 (1989-09-01), Nakazato et al.
patent: 4868628 (1989-09-01), Simmons
patent: 4907059 (1990-03-01), Kobayashi et al.
patent: 4954865 (1990-09-01), Rokos
"A Subnanosecond Low Power Advanced Bipolar-SMOS Gate Array", International Conference on Computer Design, 1984, pp. 428-433.

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