Fishing – trapping – and vermin destroying
Patent
1989-07-21
1991-06-25
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437161, 437162, 437156, 437157, 437233, H01L 21225
Patent
active
050266632
ABSTRACT:
A method of fabricating a semiconductor structure having self-aligned diffused junctions is provided wherein a first dielectric layer, a doped semiconductor layer and a second dielectric layer are formed on a semiconductor substrate. An opening extending to the semiconductor substrate is then formed through these layers. Undoped semiconductor spacers are formed in the opening adjacent to the exposed ends of the doped semiconductor layer and dopant is diffused from the doped semiconductor layer through the undoped semiconductor spacers and into the semiconductor substrate to form junctions therein. This provides for integrated contacts through the doped semiconductor layer.
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"A Novel CMOS Structure with a Reduced Drain-Substrate Capacitance"; Sagara et al; IEEE Transactions on Electronic Devices, vol. 36, No. 3, p. 598, Mar. 1989.
Vasquez Barbara
Zdebel Peter J.
Dang Trung
Hearn Brian E.
Motorola Inc.
Wolin Harry A.
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