Memory address translation system for accessing memory locations

Details Memory address translation system for accessing memory locations Memory address translation system for accessing memory locations

1981-03-16

1984-02-21

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 700, G06F 738, G06F 750

Patent

active

044333897

ABSTRACT:
In a named data processing system having a plurality of memory modules, each module therein having a plurality of locations for storing data pages and the like, a memory address translation apparatus and method translates a data job name and associated segmented address field into a memory module-page addressing pair wherein each and every storage location may be accessed by each and every job name. The job name and the associated segmented address field are each partitioned into most and least significant bit fields. Through translation a storage location is defined by the exclusive ORing of the least significant fields of the data job name and segmented address field. Likewise a memory module is defined by the exclusive ORing of the most significant fields of the job name and the segmented address field as permuted by an exclusive ORing with the least significant field of the segmented address field. Preferably, in order to increase address spacing activity, the most significant field of the job name is processed through a Fibonacci hashing process before any exclusive ORing process.

REFERENCES:
patent: 3949370 (1976-04-01), Reyling et al.
patent: 3980874 (1976-09-01), Vora
patent: 4158227 (1979-06-01), Baxter et al.
patent: 4161036 (1979-07-01), Morris et al.

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