Semiconductor arrangement with depletion layer majority carrier

Details Semiconductor arrangement with depletion layer majority carrier Semiconductor arrangement with depletion layer majority carrier

1987-11-09

1990-11-27

Jackson, Jr., Jerome

357 15, 357 16, H01L 2980, H01L 29201

Patent

active

049740377

ABSTRACT:
The invention relates to a semiconductor arrangement consisting of a semiconductor substrate and arranged thereon a conductive semiconductor layer on which at least two ohmic connection electrodes are arranged in spaced lateral relationship to each other. The invention resides in selecting the conductive layer so thin that a depletion layer formed in the semiconductor layer between the ohmic connection electrodes produces, in the semiconductor layer, a potential distribution which acts as a majority carrier barrier.

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