Sense circuit for use in semiconductor memory

Details Sense circuit for use in semiconductor memory Sense circuit for use in semiconductor memory

Filed on

1989-07-11

Date issued

1990-11-27

Examiner

Miller, Stanley D.

Patent Class

Electrical transmission or interconnection systems

SubClass

Nonlinear reactor systems

SubSubClass

Parametrons

Other Related Categories

307279, 365205, 36518905, H03K 1704, H03K 3356, H03K 1901, G11C 700

Type

Patent

Status

active

Patent number

049738640

Description

ABSTRACT:
A sense circuit includes first and second input nodes, first and second output nodes, first to fifth MOSFETs of N-channel type, and first and second potential setting circuits, and the first and second output nodes are precharged to a power source potential by the first and second potential setting circuits before the sensing operation is started. After this, the first MOSFET is turned on by a control signal to start the sensing operation. After the sensing operation is started, the potentials of the first and second input nodes are respectively amplified by the second and third MOSFETs and the fourth and fifth MOSFETs and the amplified potentials are derived from the first and second output nodes.

REFERENCES:
patent: 4494020 (1985-01-01), Konishi
patent: 4606012 (1986-08-01), Koshizuka
patent: 4616148 (1986-10-01), Ochii et al.
patent: 4816706 (1989-03-01), Dhong et al.
patent: 4831287 (1989-05-01), Golab
patent: 4843264 (1989-06-01), Galbraith
patent: 4845675 (1989-07-01), Krenik et al.
patent: 4871978 (1989-10-01), Galbraith
patent: 4894559 (1990-01-01), Kaneko
Zairyo, Denshi, Cache Unit; Y. Tanaka, pp. 146-153, Jun. 1987.
Matsui, M. et al., A 25-ns 1-Mbit CMOS SRAM with Loading-Free Bit Lines, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987.

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