Shared memory architecture of graphics frame buffer and hard dis

Details Shared memory architecture of graphics frame buffer and hard dis Shared memory architecture of graphics frame buffer and hard dis

Filed on

1995-07-18

Date issued

1997-10-28

Examiner

Tung, Kee M.

Other Related Categories

395501, 395521, 395480, G06F 15167

Type

Patent

Status

active

Patent number

056825226

Description

ABSTRACT:
A shared memory architecture of graphics frame buffer and hard disk cache is presented. The architecture includes a system bus interface, a hard disk controller, a graphics controller, an arbiter, a memory and a shared memory block. The shared memory block is divided into graphics frame buffer memory and hard disk controller cache memory. The arbiter determines the shared memory access priority between the graphics controller and the hard disk controller. By mean of hardware implementation, memories can be shared by the graphics controller and the disk controller. The complexity of the system is reduced and the system performance is enhanced. The overall system cost is decreased.

REFERENCES:
patent: 5388207 (1995-02-01), Chia et al.
patent: 5450542 (1995-09-01), Lehman et al.

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