Semiconductor device and process fabrication thereof

Details Semiconductor device and process fabrication thereof Semiconductor device and process fabrication thereof

1990-06-29

1991-06-04

James, Andrew J.

357 231, 357 233, 357 2312, 357 41, 357 55, 357 90, H01L 2910, H01L 2906, H01L 2701

Patent

active

050218450

ABSTRACT:
An insulated-gate field-effect transistor device characterized by the channel region consisting of the intermediate heavily doped portion (50; 72) and two lightly doped portions (46, 48; 74,76) provided on both sides of the heavily doped portion. Such a field-effect transistor device is advantageous in that it provides a surface potential locally increased to act as an energy barrier to minority carriers. This permits control over the threshold voltage of a MOS transistor or over the punch-through current of a punch-through transistor without having recourse to the use of a high carrier density throughout the channel region. The carrier density of the channel region being rather reduced, not only reduction in leakage current but improvement in withstand voltage characteristics can be achieved in a device according to the present invention. Where the transistor device is implemented as a trench-type device, the channel region composed of the differentially doped three portions is formed along a side wall of a trench in the substrate.

REFERENCES:
patent: 3924265 (1975-12-01), Rodgers
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patent: 4112455 (1978-09-01), Seliger et al.
patent: 4198252 (1980-04-01), Hsu
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patent: 4644386 (1987-02-01), Nishizawa et al.
patent: 4786953 (1988-11-01), Morie et al.
A Trench Mosfet with Surface Source/Drain Contacts, by Shigeru Nakajima, Kenji Miura, Toshifumi Somatani and Eisuke Arai, May 1985, IEDM Publication, pp. 200-203.

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