High speed memory and processor system for raster display

Details High speed memory and processor system for raster display High speed memory and processor system for raster display

1984-05-23

1987-03-03

Wise, Edward J.

Boots, shoes, and leggings

364521, 340799, G06F 1520, G06F 314, G09G 100

Patent

active

046480455

ABSTRACT:
Disclosed is a high speed memory system having a parallel architecture which is particularly advantageous in controlling a multiline raster scanned display. Data for a plurality of scan lines is processed in parallel, and pixel data for each of a plurality of scan lines is stored in a plurality of memory segments which can be accessed in parallel. Latch means is provided with each memory segment for latching pixel data for scan line control in order to allow continued manipulation of data stored in the memory segment while scan line data is extracted. A plurality of scan line processors are connected to a common bus which provides transformed data of primitives in display coordinates. Each scan line processor controls data for a plurality of scan lines, and a plurality of memory segments are connected with each scan line processor for storing and manipulating pixel data for the plurality of scan lines. Each memory segment includes a random access storage array and an arithmetic logic unit responsive to scan line number, start point, and end point data from the scan line processor for storing and accessing data in the random access storage array. The arithmetic logic unit is responsive to halftone pattern data or smoothly interpolated intensity data and commands for performing Boolean logical operations on stored data.

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