Low power decoder-driver circuit

Details Low power decoder-driver circuit Low power decoder-driver circuit

1983-08-31

1986-09-09

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307270, 365227, 365230, H03K 19094, H03K 1920, G11C 800

Patent

active

046111310

ABSTRACT:
A memory decoder wherein a power-up device is interposed between a NOR decoder and ground (VSS), rather than between the decoder and VDD. Preferably the signal to the power-up transistor is itself decoded, so that the power-consuming NOR circuits are inactive over a majority of the chip, even during power-up conditions.

REFERENCES:
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4099162 (1978-07-01), Basse
patent: 4200917 (1980-04-01), Moench
patent: 4272834 (1981-06-01), Noguchi et al.
patent: 4301535 (1981-11-01), McKenny
patent: 4393472 (1983-07-01), Shimada et al.
patent: 4401903 (1983-08-01), Iizuka

Affiliated with

Also associated with

Rating

Low power decoder-driver circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power decoder-driver circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power decoder-driver circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1016582