Patent
1988-09-08
1991-11-12
Prenty, Mark
357 40, H01L 2348, H01L 2702
Patent
active
050652249
ABSTRACT:
To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe. An additional lead is obtained from a conductive element originating near the paddle and supported by one of the two lead frame rails.
REFERENCES:
patent: 4613771 (1986-09-01), Gal
patent: 4654549 (1987-03-01), Hannington
patent: 4680613 (1987-07-01), Daniels et al.
Patent Abstracts of Japan, vol. 6, No. 103 (E-112)[981] 12th Jun. 1982; JP-A-57 035361 (Nippon Denki K.K.) 25-02-1982.
Fairchild Camera & Instrument Corp., ECL Data Book, 1977, pp. 2.3-2.4, Mountain View, California U.S.
Patent Abstracts of Japan, vol. 10, No. 343 (E-456) [2399], 19 Nov. 1986; JP-A-61 147 559 (NEC Corp.) 05-07-1986.
Fraser Dana
Gray Jerry
Hannington Geoff
Keown Susan M.
Mathieu Gaetan L.
Fairchild Semiconductor Corporation
Kane Daniel H.
Prenty Mark
Rose James W.
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