1990-05-31
1991-11-12
James, Andrew J.
357 71, H01L 2710, H01L 2348
Patent
active
050652230
ABSTRACT:
A semiconductor device includes a semiconductor chip, a substrate for supporting the semiconductor chip, a plurality of terminals provided on the substrate for external connections, a plurality of lead wires provided on the semiconductor chip for connections to the terminals, and a multilevel interconnection structure for connecting the plurality of terminals to the plurality of lead wires on the semiconductor chip. The multilevel interconnection structure includes at least a lower conductor layer provided on the substrate and patterned into a plurality of pattern portions connected electrically to the terminals, an insulator layer provided on the lower conductor layer, and an upper conductor layer provided above the insulator layer. The upper conductor layer is formed with a connection area immediately below the lead wires on the semiconductor chip when the semiconductor chip is mounted on the substrate, the upper conductor layer is patterned in the connection area into a plurality of conductor strips extending parallel with each other in correspondence to the lead wires, the insulator layer is provided with contact holes so as to connect electrically the conductor strips of the upper conductor layer with the pattern portions of the lower conductor layer. In the semiconductor device, each of the pattern portions in the connection area has an edge extending obliquely to the conductor strips of the upper conductor layer wherein the pattern portions are disposed so that a pair of adjacent pattern portions have respective edges opposing with each other and extending parallel with each other with a lateral gap extending therebetween.
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Harada Shigeki
Matsuki Hirohisa
Sugimoto Masahiro
Yoshida Toshiki
Fujitsu Limited
Fujitsu VLSI Limited
James Andrew J.
Nguyen Viet Q.
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