Programmable data port clocking system for clocking a plurality

Details Programmable data port clocking system for clocking a plurality Programmable data port clocking system for clocking a plurality

1995-06-07

1997-10-21

Lee, Thomas C.

395556, 395560, 395551, G06F 1500

Patent

active

056805950

ABSTRACT:
A programmable multiconfiguration data port clocking system for use in asynchronous transfer mode communication (ATM) networks. The clocking system is programmed using a number of preselected configuration codes to automatically switch the clocking of the data port configuration of an ATM network chip. The clocking system incorporates an automatic disable circuit for eliminating random outputs from unused pins in the clocking hardware. The clocking system also employs a noise suppression circuit for reducing spurious noise into the ATM network.

REFERENCES:
patent: 4631702 (1986-12-01), Korba
patent: 4701747 (1987-10-01), Isherwood et al.
patent: 4891794 (1990-01-01), Hush et al.
patent: 5444700 (1995-08-01), Martikainen et al.
A 0.8-um BiCMOS ATM Switch on an 800-Mb/s Asynchronous Buffered Banyan Network IEEE Journal of Solid-State Circuits vol. 26, No. 8, Aug. 1991., Kenji Sakaue et al.

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