Fabrication of stud-defined integrated circuit structure

Details Fabrication of stud-defined integrated circuit structure Fabrication of stud-defined integrated circuit structure

1985-05-28

1987-03-10

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29576B, 29576E, 148 15, 148175, 148187, 357 50, H07L 2120, H07L 2128

Patent

active

046481737

ABSTRACT:
Fabrication of a submicron wide single crystal silicon structure protruding from a monolithic silicon body. Starting with a single crystal N silicon body having a P region, an insulator stud of submicron width and length dictated by the limits of lithography is formed on the P region. Using the stud as a mask, the P region is etched forming the top narrow portion having the stud width projecting from the silicon body. On the exposed sides of the top portion oxide walls are formed and the etching continued forming the middle portion of a width exceeding that of the top portion. An oxide-nitride wall is established on the exposed sides of the middle portion and, using the resulting structure as a mask, the etching is continued to completely etch through the P region and a substantial portion of the underlying N silicon body thereby forming a free-standing silicon protrusion structure. Thick oxide walls are formed on the just exposed sides of the silicon. Alternatively, the exposed sides of silicon may be completely oxidized to obtain a fully dielectrically isolated silicon protruding structure.
To form NPN device from the silicon protrusion structure, the oxide-nitride walls corresponding to the middle portion are removed and N-type dopant is introduced from the thus exposed sides forming the emitter and collector juxtaposed on either side of the central P-type region which functions as the base. Self-aligned metal contacts to the elements of the transistor are established on the top and sides.

REFERENCES:
patent: 3648125 (1972-03-01), Peltzer
patent: 4095330 (1978-06-01), Kim
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4104090 (1978-08-01), Pogge
patent: 4211582 (1980-07-01), Horng et al.
patent: 4400865 (1983-08-01), Goth et al.
patent: 4430791 (1984-02-01), Dockerty
patent: 4444605 (1984-04-01), Slawinski
patent: 4502913 (1985-03-01), Lechaton et al.
patent: 4508579 (1985-04-01), Goth et al.
patent: 4510016 (1985-04-01), Chi et al.
patent: 4549927 (1985-10-01), Goth et al.
patent: 4561932 (1985-12-01), Gris et al.
patent: 4572765 (1986-02-01), Berry
S. D. Malaviya, "High Speed Bipolar Process", IBM Technical Disclosure Bulletin vol. 27, No. 7B, Dec. 1984, pp. 4510-4514.
S. D. Malaviya, "Metal Lift-Off Process for Submicron Spacings", IBM Technical Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 1063-1065.

Affiliated with

Also associated with

Rating

Fabrication of stud-defined integrated circuit structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication of stud-defined integrated circuit structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of stud-defined integrated circuit structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1015108