Integrated semiconductor circuit having scan flip-flops at prede

Details Integrated semiconductor circuit having scan flip-flops at prede Integrated semiconductor circuit having scan flip-flops at prede

1994-08-17

1997-10-21

Beausoliel, Jr., Robert W.

Excavating

G01R 3128

Patent

active

056804067

ABSTRACT:
An integrated semiconductor circuit and a testing method thereof to achieve a reduced chip area and a shorter test time. In the circuit, scan flip-flops occur at regular intervals. In the exemplary case, supposing a third flip-flop is defective and constantly outputs a 0, firstly a data value 1 is scanned into a second flip-flop, and then under a normal operation mode the data of the second flip-flop is transmitted to the third, before a scan-out action thereof, which permits the detect of the third flip-flop to be detected. When supposing a fifth flip-flop is similarly defective, a first scan-in action is performed to input a data value 1 to a second and a fourth flip-flop, and the data are transmitted to the third and the fifth flip-flop. Then, a second scan-in is performed to input 0 to the fifth flip-flop, before a scan-out action of data, which permits the trouble of the fifth flip-flop to be detected.

REFERENCES:
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patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5130647 (1992-07-01), Sakashita et al.
patent: 5254942 (1993-10-01), D'Souza et al.
patent: 5341096 (1994-08-01), Yamamura

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