Circuit and method for accessing memory cells of a memory device

Details Circuit and method for accessing memory cells of a memory device Circuit and method for accessing memory cells of a memory device

1996-05-30

1997-10-21

Nelms, David C.

Static information storage and retrieval

Addressing

36523006, 36523008, 365201, G11C 800, G11C 700

Patent

active

056803621

ABSTRACT:
A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.

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patent: 5313425 (1994-05-01), Lee et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5394373 (1995-02-01), Kawamoto
patent: 5406526 (1995-04-01), Sugibayashi et al.

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