Method for narrowing threshold voltage distribution in a block e

Static information storage and retrieval – Floating gate – Particular biasing

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36518529, 36518533, G11C 1134

Patent

active

056803508

ABSTRACT:
This invention constitutes a method for narrowing threshold voltage distribution among the individual cells of a block erased flash memory array by firstly, preprogramming cells within the block be erased to a level of saturation using hot electron injection to drive a surplus of electrons into the floating gate of each cell; secondly, subjecting all cells with the block to a first erase pulse which causes the surplus electrons within the floating gate of each cell to be driven into the cell's source region via Fowler-Nordheim tunneling, with the erase pulse being of sufficient length to erase every cell within the block; thirdly, subjecting all cells within the block to a word line stress step or a soft programming step, by means of which some electrons are driven back into the floating gate of each cell via Fowler-Nordheim tunneling or hot electron injection, respectively; and, fourthly, subjecting all cells within the block to a second erase pulse, the second erase pulse being at least an order of magnitude shorter than the first erase pulse. Use of the second erase pulse following the word line stress step not only shifts the threshold voltage distribution to a somewhat lower level, but also compresses the distribution. Since compression on the high side of the curve is greater than on the low side, the length of the second erase pulse can be tailored to fit the characteristics of a particular flash memory.

REFERENCES:
patent: 5295107 (1994-03-01), Okazawa et al.
patent: 5313427 (1994-05-01), Schreck
patent: 5347490 (1994-09-01), Terada et al.
patent: 5400286 (1995-03-01), Chu et al.
patent: 5452248 (1995-09-01), Narwke et al.

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